1. Field of the Invention
The invention generally relates to interface systems for interfacing a computer system host to an asynchronous transfer mode (ATM) system and, in particular, to a method and apparatus for synthesizing clock signals for use with an ATM system capable of operating at two-data transmission rates.
2. Description of Related Art
ATM technology is emerging as the preferred technology for implementing broadband integrated services data networks ISDNs (B-ISDN). A B-ISDN is a system for interconnecting computer systems, local area networks (LANs), telephones, facsimiles, etc., to facilitate communication of data, voice and video between the systems. B-ISDN typically employs fiber optics as a communication medium. An ATM system facilitates the transmission of data over the B-ISDN by defining a set of "data connections" where each connection represents a virtual circuit having a particular source and destination and an associated data transmission rate.
Data provided by a computer system, LAN, telephone, etc., may initially be stored in packets of data. ATM technology, however, requires the data to be stored and processed within cells of data. Accordingly, a method or apparatus must be provided for segmenting packets into cells and for reassembling cells into packets. Typically, a segmentation and reassembly (SAR) application specific integrate circuit (ASIC) chip is provided for connecting the computer system to an ATM system.
One particular implementation of an ATM system employs a physical layer (PHY) chip configured to implement a Universal Test and Operational Physical Interface (UTOPIA) protocol. The PHY chip operates as a "front end" to the overall ATM system. For ATM, the PHY chip is typically a Synchronous Optical Network (SONET) framer and is connected to a fiber optic line. The PHY chip receives cells from the SAR chip for transference to other PHY chips. The PHY chip also receives cells along the fiber optic line for forwarding to the SAR chip for reassembly into packets for eventual transference to the computer system or LAN.
In this arrangement, the SAR chip operates as a master and the PHY chip operates as a slave. For example, to transfer data from the PHY chip to the SAR chip, the PHY chip provides a signal indicating that the PHY chip has data available. The SAR chip then initiates actual transference of the data from the PHY chip. Likewise, to transfer data from a SAR chip to PHY chip, the SAR chip initiates the transference.
A PHY chip employing the UTOPIA protocol is capable of operating at either 155 megabits per second (Mbps) or 622 Mbps. 155 Mbps is achieved using a 20-25 megahertz (MHz) clock signal whereas 622 Mbps is achieved using a 40-50 MHz clock signal. (Actually, 155 Mbps may be achieved using a 19.44 MHz clock signal and 622 Mbps may be achieved using a 38.88 MHz signal. These frequencies represent the lowest frequencies with which the corresponding Mbps data transfer rate may be achieved. The 25 MHz and 50 MHz limits are protocol limits defined by the UTOPIA specification.) The PHY chip is configured to receive the appropriate clock signal, whether 20-25 MHz or 40-50 MHz, from the ATM system through a single pair of clock pins (R.sub.- CLK and T.sub.- CLK). The PHY chip is also configured to receive a variety of other signals including data and control signals which are associated either with R.sub.- CLK or T.sub.- CLK.
Conventional SAR chips for use with a UTOPIA PHY chip operate only at 155 Mbps and provide only a 20 MHz signal to the PHY chip. It is anticipated that 622 Mbps SAR chips will be developed which operate only at 622 Mbps by operating internally at 40-50 MHz while also driving the PHY chip at 40-50 MHz.
It would be desirable, however, to provide an SAR chip for use with a UTOPIA, or similar, PHY chip which is capable of operating at either 155 Mbps or 622 Mbps. A significant problem, however, in providing such an SAR chip is accounting for the two different required clock rates. More specifically, a method or protocol is required for allowing data to be clocked out of the SAR chip and thereafter unambiguously sampled by the PHY chip and vice versa. This is particularly problematic because of possible phase delays, of generally unknown duration, occurring between the clock signals operating internally within the SAR chip and the actual clock driving signals received by the PHY chip. In other systems, similar phase or timing delays are accounted for by iteratively tuning the relative phases of the separate systems, perhaps by inserting various delay lines, etc. The need to iteratively tune a system, however, adds to the overall cost of developing the system. Accordingly, it is also desirable to provide a system for interfacing with a PHY chip, or similar, which is not only capable of operating at either 155 Mbps or 622 Mbps but which also allows data to be clocked and sampled unambiguously without requiring conventional iterative tuning techniques. In other words, it is desirable to provide a system design solution, rather than a iterative tuning solution, for ensuring unambiguous data transfer. It is to these ends that aspects of the present invention are drawn.